Experience & Projects
RISC-V SoC on FPGA
01/2026
Student Intern · RPTU Kaiserslautern-Landau
- PicoRV32-based RISC-V SoC on Intel FPGA with 32 MB SDRAM, SPI flash, and VGA framebuffer.
- Multi-stage bootloader pipeline (BRAM → SDRAM → Flash) with Execute-In-Place (XIP).
- RTL design, synthesis, place-and-route, and hardware bring-up.
Independent Hardware & Security Engineering
2023 — Present
Self-directed · Kaiserslautern, DE
- 6-layer PCB design (controlled impedance, MIPI-CSI2) manufactured via JLCPCB/PCBWay.
- Web/API vulnerability research via Intigriti VDP and private programs.
- NXP chip-sampling sponsorships.
- NXP chip-sampling partnership and prototyping sponsorships.
- Radiacode Sponsoring for desk sized CT-scanner project
BitBreach — RF & Security Hardware
2024 — 2025
github.com/Luka-io/Bitbreach · 21 ★
- ESP32-S3 + STM32G4 multi-MCU board with CC1101, LLCC68 LoRa, and PN7150 NFC.
- 6-layer KiCad board with RF controlled impedance routing.
- Sponsored by JLCPCB, PCBWay, and NXP Semiconductors.
Security Research
Platform: Intigriti — coordinated disclosure under VDP terms. Standards: CVSS v3.1 / v4.0 (FIRST.org).
Public Programs (VDP)
#1 Revolut VDP (2025)
10.0 Braintags: Critical auth-bypass & privilege-escalation chain.
Private Programs (Invite-only)
AutoScout24
DKV Mobility
R+V Versicherung
More
Technical Skills
Electrical Design
FPGA / Digital
Embedded
Security
RF / Wireless
Education & Languages
Abitur (Expected 2028)
Gymnasium am Rittersberg · Kaiserslautern, DE
Languages